High Performance Embedded Architectures And Compilers 5th International Conferen

Invited Program.- Embedded Systems As Datacenters.- Larrabee: A Many-core Intel Architecture For Visual Computing.- Architectural Support For Concurrency.- Remote Store Programming.- Low-overhead, High-speed Multi-core Barrier Synchronization.- Improving Performance By Reducing Aborts In Hardware Transactional Memory.- Energy And Throughput Efficient Transactional Memory For Embedded Multicore Systems.- Compilation And Runtime Systems.- Split Register Allocation: Linear Complexity Without The Performance Penalty.- Trace-based Data Layout Optimizations For Multi-core Processors.- Buffer Sizing For Self-timed Stream Programs On Heterogeneous Distributed Memory Multiprocessors.- Automatically Tuning Sparse Matrix-vector Multiplication For Gpu Architectures.- Reconfigurable And Customized Architectures.- Virtual Ways: Efficient Coherence For Architecturally Visible Storage In Automatic Instruction Set Extensions.- Accelerating Xml Query Matching Through Custom Stack Generation On Fpgas.- An Application-aware Load Balancing Strategy For Network Processors.- Memory-aware Application Mapping On Coarse-grained Reconfigurable Arrays.- Multicore Efficiency, Reliability, And Power.- Maestro: Orchestrating Lifetime Reliability In Chip Multiprocessors.- Combining Locality Analysis With Online Proactive Job Co-scheduling In Chip Multiprocessors.- Relocate: Register File Local Access Pattern Redistribution Mechanism For Power And Thermal Management In Out-of-order Embedded Processor.- Performance And Power Aware Cmp Thread Allocation Modeling.- Memory Organization And Optimization.- Multi-level Hardware Prefetching Using Low Complexity Delta Correlating Prediction Tables With Partial Matching.- Scalable Shared-cache Management By Containing Thrashing Workloads.- Srp: Symbiotic Resource Partitioning Of The Memory Hierarchy In Cmps.- Dief: An Accurate Interference Feedback Mechanism For Chip Multiprocessor Memory Systems.- Programming And Analysis Of Accelerators.- Tagged Procedure